-
FPGA1
- Wrapper module for FPGA1 (CORE).
module fpga1_1_0 (
addbus, specmode, vectorfe, writdb, readwrit, size8, stopmode, waitmode, perisel, ramrgsel, ramarsel, feergsel, feearsel, eeregsel, eearrsel, secureo, porta, portb, porte, portk, mdrste, bdmact, bkgdebug, wakup_ta, xab, rst_ta, clk23, clk24, clk34, oscclk, testclk, testclke, copvrqes, rstvrqes, xmonrqes, pllsel, rstpin_b, testmode, romonsta, reg_sw0, pag_sw1, pag_sw0, ram_sw2, ram_sw1, ram_sw0, rom_sw1, rom_sw0, eep_sw1, eep_sw0, feehold, eehold, securei, readdb, pe_ind, cwait, sywait, rtifff0i, ffxx
);
/****************************************************************************/
/* PARAMETERS */
/****************************************************************************/
parameter GBW = 8; // data bitwidth
parameter GABW = 16; // address bitwidth
parameter GIBW = 37; // interrupt bitwidth
/****************************************************************************/
/* PORTS */
/****************************************************************************/
output [15:0] addbus;
output specmode;
output vectorfe;
output [15:0] writdb;
output readwrit;
output size8;
output stopmode;
output waitmode;
output perisel;
output ramrgsel;
output ramarsel;
output feergsel;
output feearsel;
output eeregsel;
output eearrsel;
output secureo;
inout [7:0] porta;
inout [7:0] portb;
inout [7:2] porte;
inout [7:0] portk;
output mdrste;
output bdmact;
inout bkgdebug;
output wakup_ta;
output [19:14] xab;
input rst_ta;
input clk23;
input clk24;
input clk34;
input oscclk;
input testclk;
input testclke;
input copvrqes;
input rstvrqes;
input xmonrqes;
input pllsel;
input rstpin_b;
input testmode;
input romonsta;
input reg_sw0;
input pag_sw1;
input pag_sw0;
input ram_sw2;
input ram_sw1;
input ram_sw0;
input rom_sw1;
input rom_sw0;
input eep_sw1;
input eep_sw0;
input feehold;
input eehold;
input securei;
input [15:0] readdb;
input [1:0] pe_ind;
input cwait;
input sywait;
input rtifff0i;
input [GIBW-1:0] ffxx;
/****************************************************************************/
/* SIGNALS */
/****************************************************************************/
wire [7:0] pado;
wire [7:0] pahiz;
wire [7:0] pbdo;
wire [7:0] pbhiz;
wire [7:2] pedo;
wire [7:2] pehiz;
wire [7:0] pkdo;
wire [7:0] pkhiz;
wire [7:0] pa_ind;
wire [7:0] pb_ind;
wire [7:0] pe_indata;
wire [7:0] pk_ind;
wire bkgddout;
wire bkgd_hiz_t4;
wire bkgd_ind;
/****************************************************************************/
/* RTL */
/****************************************************************************/
assign pe_indata[1:0] = pe_ind[1:0];
// bitwise enabled bidirectional pads
bidirec8 PA_PAD (.oe(pahiz), .inp(pa_ind), .outp(pado), .bidir(porta) );
bidirec8 PB_PAD (.oe(pbhiz), .inp(pb_ind), .outp(pbdo), .bidir(portb) );
bidirec6 PE_PAD (.oe(pehiz), .inp(pe_indata[7:2]), .outp(pedo), .bidir(porte) );
bidirec8 PK_PAD (.oe(pkhiz), .inp(pk_ind), .outp(pkdo), .bidir(portk) );
bidirec BKGD_PAD (.oe(bkgd_hiz_t4), .inp(bkgd_ind), .outp(bkgddout), .bidir(bkgdebug) );
core CORE (
.core_ab_t2 (addbus[GABW-1:0]),
.core_rw_t2 (readwrit),
.core_smod_t2 (specmode),
.core_sz8_t2 (size8),
.core_stop_t24 (stopmode),
.core_wait_t24 (waitmode),
.core_perisel_t2 (perisel),
.core_ramregsel_t2 (ramrgsel),
.core_ramarraysel_t2 (ramarsel),
.core_feeregsel_t2 (feergsel),
.core_feearraysel_t2 (feearsel),
.core_eeregsel_t2 (eeregsel),
.core_eearraysel_t2 (eearrsel),
.core_secure_t2 (secureo),
.core_pado (pado),
.core_pahiz (pahiz),
.core_papue_t2 (), // removed
.core_pard_t2 (), // removed
.core_pbdo (pbdo),
.core_pbhiz (pbhiz),
.core_pbpue_t2 (), // removed
.core_pbrd_t2 (), // removed
.core_pedo (pedo),
.core_pehiz (pehiz),
.core_pepue_t2 (), // removed
.core_perd_t2 (), // removed
.core_pkdo (pkdo),
.core_pkhiz (pkhiz),
.core_pkpue_t2 (), // removed
.core_pkrd_t2 (), // removed
.core_mdrste (mdrste),
.core_bdmact_t4 (bdmact),
.core_bkgd_dout_t4 (bkgddout),
.core_bkgd_hiz_t4 (bkgd_hiz_t4),
.core_bkgd_ibe_t2 (), // removed
.core_vector_fetch_t4 (vectorfe),
.core_wdb_t4 (writdb),
.core_wakeup_ta (wakup_ta),
.core_xab_t2 (xab),
.peri_reset_ta4 (rst_ta),
.peri_clk23 (clk23),
.peri_clk24 (clk24),
.peri_clk34 (clk34),
.peri_oscclk (oscclk),
.peri_test_clk (testclk),
.peri_test_clk_enable (testclke),
.peri_copv_request (copvrqes),
.peri_rstv_request (rstvrqes),
.peri_xmonv_request (xmonrqes),
.peri_pllsel_t3 (pllsel),
.reset_pin_input_b (rstpin_b),
.bkgd_ind (bkgd_ind),
.test_mode_en (testmode),
.romon_exp_state (romonsta),
.reg_sw0 (reg_sw0),
.pag_sw1 (pag_sw1),
.pag_sw0 (pag_sw0),
.ram_sw2 (ram_sw2),
.ram_sw1 (ram_sw1),
.ram_sw0 (ram_sw0),
.rom_sw1 (rom_sw1),
.rom_sw0 (rom_sw0),
.eep_sw1 (eep_sw1),
.eep_sw0 (eep_sw0),
.fee_hold_t1 (feehold),
.ee_hold_t1 (eehold),
.secure (securei),
.ee_rdb_L12 (readdb),
.fee_rdb_L12 (readdb),
.ram_rdb_L12 (readdb),
.peri_rdb_L12 (readdb),
.pa_ind (pa_ind),
.pb_ind (pb_ind),
.pe_ind (pe_indata),
.pk_ind (pk_ind),
.peri_cwai_t3 (cwait),
.peri_syswai_t3 (sywait),
.peri_rtifff0i_t3 (rtifff0i),
.peri_ffxx_t3 ({{(55-GIBW+1){1'b0}}, ffxx})
);
endmodule // fpga1_1_0
-
FPGA2
- Wrapper module for FPGA2 (Interface modules).
/*+FHDR**********************************************************************/
/* Copyright (c) 1997, Motorola. */
/* Motorola Confidential Proprietary */
/****************************************************************************/
// FILE NAME : pif_kd128.v
// DEPARTMENT : MCU Design Center, Munich
// EMAIL : Andreas_Tuechler-R7906C@email.sps.mot.com
/****************************************************************************/
// version tag, generated by version control software
/****************************************************************************/
// Release history
// VERSION Date AUTHOR DESCRIPTION
// 1.2 12 Aug 1999 andreast added timer module
// 1.1 06 Aug 1999 andreast integrated IPbus interface
// 1.0 26 Jul 1999 andreast initial version
//
/****************************************************************************/
// NAMES(TYPE) : pif_1_0(module)
/****************************************************************************/
// KEYWORDS : wrapper module for SCI, SPI, I2C, BDLC, PWM, TIMER
// PURPOSE : FPGA emulation
/****************************************************************************/
// GLOBAL VARIABLES
// USED : none
// DEFINED : none
//
// DEPENDENCIES
// Verilog Version : XL 2.2.27
// Tools : Synopsys 1997.01
// Libraries : flex10k
// Other :
/*-FHDR**********************************************************************/
module pif_1_0 (
// IPbus-CLOCKS & RESETS
clk,
bus_clk,
clk34,
hard_rst_b,
// IPbus-DATA BUSSES
data_wr,
data_rd,
// IPbus-PROTOCOL SIGNALS
addr,
byte_en_7_0_b,
byte_en_15_8_b,
read_en_b,
write_en_b,
// module enable signals
sci1_en_b,
sci2_en_b,
spi_en_b,
i2c_en_b,
bdlc_en_b,
pwm_en_b,
tim_en_b,
// IPbus-MODE SIGNALS
freeze_mode,
stop_mode,
wait_mode,
test_mode,
scanmod,
// IPbus-INTERRUPT SIGNALS
int_b,
rd_int_vector_b,
// Output port for SCI module
scrReadSCI,
pclRdiOut,
pclTdoOut,
scrWoms,
scrScSWai,
// Input port for SCI module
vddpll,
ptRdi,
ptTdo,
// Output port for SPI module
scrReadSPI,
pclSsbOut,
pclSclkOut,
pclMosiOut,
pclMisoOut,
scrSwom,
// Input port for SPI module
ptSsb,
ptSclk,
ptMosi,
ptMiso,
// port for I2C module
sclOut,
sclIn,
sdaOut,
sdaIn,
// port for BDLC module
dlc_do_t4,
dlcp_ind,
// port for PWM module
pwm_do_t4,
pwmp_ind,
// Output port for TIMER modulevsc
timp_ind,
vsc_scane,
// Input port for CRG module
osc_clk
) ;
/****************************************************************************/
/* PARAMETERS */
/****************************************************************************/
parameter GDBW = 16; // data bitwidth
parameter GABW = 16; // address bitwidth
parameter GIBW = 16; // interrupt bitwidth
parameter GBW = 8; // 8 bit data bitwidth
/****************************************************************************/
/* PORTS */
/****************************************************************************/
// IPbus-CLOCKS & RESETS
input clk;
input bus_clk;
input clk34;
input hard_rst_b;
// IPbus-DATA BUSSES
output [GDBW-1:0] data_rd;
input [GDBW-1:0] data_wr;
// IPbus-MODE SIGNALS
input [GABW-1:0] addr;
input byte_en_7_0_b;
input byte_en_15_8_b;
input read_en_b;
input write_en_b;
// module enable signals
input sci1_en_b; // SCI1 module select
input sci2_en_b; // SCI2 module select
input spi_en_b; // SPI module select
input i2c_en_b; // I2C module select
input bdlc_en_b; // BDLC module select
input pwm_en_b; // PWM module select
input tim_en_b; // TIMER module select
// IPbus-MODE SIGNALS
input freeze_mode;
input stop_mode;
input wait_mode;
input test_mode;
input scanmod;
// IPbus-INTERRUPT SIGNALS
output [GIBW-1:0] int_b;
input rd_int_vector_b;
// Parameters of SCI module
parameter OFSSCI = 5'b11111; // the offset is overwritten by the instantiating module
// Port Declarations for SCI module
output scrReadSCI; // signal indicating that one SCI register is read accessed
output pclRdiOut; // SCI output data for Rdi pin
output pclTdoOut; // SCI output data for Tdo pin
input vddpll; // vddpll pin signal
input ptRdi; // Rdi pin signal
input ptTdo; // Tdo pin signal
// Port Declarations for SPI module
output scrReadSPI; // signal indicating that one SPI register is read accessed
output pclSsbOut; // SPI data Out signal for SSb pin
output pclSclkOut; // SPI data Out signal for SCLK pin
output pclMosiOut; // SPI data Out signal for MOSI pin
output pclMisoOut; // SPI data Out signal for MISO pin
output scrSwom; // SPI port Wired OR mode bit 5 of SPCR1
input ptSsb; // SSb pin signal
input ptSclk; // Sclk pin signal
input ptMosi; // MOSI pin signal
input ptMiso; // MISO pin signal
// Port Declarations for I2C module
input sclIn, // input from bi-direct scl pin
sdaIn; // input from bi-direct sda pin
output sclOut, // output to bi-direct scl pin
sdaOut; // output to bi-direct sda pin
// Port Declarations for BDLC module
output [7:0] dlc_do_t4;
input [7:0] dlcp_ind;
// Port Declarations for PWM module
input [7:0] pwmp_ind; //PWM data input
output [7:0] pwm_do_t4; //PWM data output
// Parameters of TIMER module
parameter WIDTH = 8;
// Port Declarations for TIMER module
output [WIDTH-1:0] tim_do_t4;
input [WIDTH-1:0] timp_ind;
// Port Declarations for CRG module
input osc_clk; // Oscillator Clock
//****************************************************************************/
/* SIGNALS */
/****************************************************************************/
wire [15:0] data_rd_sci1,
data_rd_sci2,
data_rd_spi,
data_rd_bdlc,
data_rd_pwm,
data_rd_tim,
data_rd_mscan;
wire [7:0] data_rd_i2c,
data_out_pwm,
data_out_bdlc,
hiz_t4_pwm,
hiz_t4_bdlc;
wire [GIBW-1:0] int; // Interrupt bus
wire rw_t2; // read/write signal
/****************************************************************************/
/* RTL */
/****************************************************************************/
// combine interrupt signals of all modules to the inverted IPbus interrupt bus
inv #(GIBW) INV1 ( .do(int_b), .di(int) );
// create single bit read/write signal
assign rw_t2 = write_en_b & ~read_en_b;
/****************************************************************************/
/* SCI1 Modules */
/****************************************************************************/
msi_sci SCI1 (
.scrReadSCI(scrReadSCI),
.pclRdiHiz(), // removed
.pclTdoHiz(), // removed
.pclRdiEn(), // removed
.pclTdoEn(), // removed
.pclRdiOut(pclRdiOut),
.pclTdoOut(pclTdoOut),
.pclRdiRst(), // removed
.pclTdoRst(), // removed
.scrWoms(scrWoms),
.scrScSWai(scrScSWai),
.scrScInt(int[0]), // old name: scrScInt
.scrData(data_rd_sci1), // old name: scrData
.mbiDb(data_wr), // old name: mbiDb
.mbiAbq(addr[4:0]), // old name: mbiAbq
.mbiRst(~hard_rst_b), // old name: mbiRst
.sciPclk(bus_clk), // old name: sciPclk
.sciMclkB(clk), // old name: sciMclkB
.mbiSz8q(byte_en_7_0_b), // old name: mbiSz8q
.mbiRwq(rw_t2), // old name: mbiRwq
.mbiMsisq(~sci1_en_b), // old name: mbiMsisq
.mbiWai(wait_mode), // old name: mbiWai
.mbiSmod(test_mode), // old name: mbiSmod
.vddpll(vddpll),
.ptRdi(ptRdi),
.ptTdo(ptTdo),
.ptRdiDdr(), // removed
.ptTdoDdr() // removed
);
/****************************************************************************/
/* SCI2 Modules */
/****************************************************************************/
msi_sci SCI2 (
.scrReadSCI(scrReadSCI),
.pclRdiHiz(), // removed
.pclTdoHiz(), // removed
.pclRdiEn(), // removed
.pclTdoEn(), // removed
.pclRdiOut(pclRdiOut),
.pclTdoOut(pclTdoOut),
.pclRdiRst(), // removed
.pclTdoRst(), // removed
.scrWoms(scrWoms),
.scrScSWai(scrScSWai),
.scrScInt(int[1]), // old name: scrScInt
.scrData(data_rd_sci2), // old name: scrData
.mbiDb(data_wr), // old name: mbiDb
.mbiAbq(addr[4:0]), // old name: mbiAbq
.mbiRst(~hard_rst_b), // old name: mbiRst
.sciPclk(bus_clk), // old name: sciPclk
.sciMclkB(clk), // old name: sciMclkB
.mbiSz8q(byte_en_7_0_b), // old name: mbiSz8q
.mbiRwq(rw_t2), // old name: mbiRwq
.mbiMsisq(~sci2_en_b), // old name: mbiMsisq
.mbiWai(mbiWai),
.mbiSmod(test_mode), // old name: mbiSmod
.vddpll(vddpll),
.ptRdi(ptRdi),
.ptTdo(ptTdo),
.ptRdiDdr(), // removed
.ptTdoDdr() // removed
);
/****************************************************************************/
/* SPI Module */
/****************************************************************************/
msi_spi SPI (
.scrReadSPI(scrReadSPI),
.pclSsbHiz(), // removed
.pclSclkHiz(), // removed
.pclMosiHiz(), // removed
.pclMisoHiz(), // removed
.pclSsbEn(), // removed
.pclSclkEn(), // removed
.pclMosiEn(), // removed
.pclMisoEn(), // removed
.pclSsbOut(pclSsbOut),
.pclSclkOut(pclSclkOut),
.pclMosiOut(pclMosiOut),
.pclMisoOut(pclMisoOut),
.pclSsbRst(), // removed
.pclSclkRst(), // removed
.pclMosiRst(), // removed
.pclMisoRst(), // removed
.scrSwom(scrSwom),
.scrSpswai(), // removed
.scrSpint(int[2]), // old name: scrSpint
.scrSpiStop(), // removed
.scrData(data_rd_spi), // old name: scrData
.mbiDb(data_wr), // old name: mbiDb
.mbiAbq(addr[4:0]), // old name: mbiAbq
.mbiRst(~hard_rst_b), // old name: mbiRst
.spiPclk(bus_clk), // old name: spiPclk
.spiT4Clk(clk), // old name: spiT4Clk
.mbiSz8q(byte_en_7_0_b), // old name: mbiSz8q
.mbiRwq(rw_t2), // old name: mbiRwq
.mbiMsisq(~spi_en_b), // old name: mbiMsisq
.mbiStop(stop_mode), // old name: mbiStop
.ptSsb(ptSsb),
.ptSclk(ptSclk),
.ptMosi(ptMosi),
.ptMiso(ptMiso),
.ptSsbDdr(), // removed
.ptSclkDdr(), // removed
.ptMosiDdr(), // removed
.ptMisoDdr() // removed
);
/****************************************************************************/
/* I2C Module */
/****************************************************************************/
mbus_sb I2C (
.dataOut(data_rd_i2c), // old name: dataOut
.dataIn(data_wr[7:0]), // old name: dataIn
.interruptB(int[3]), // old name: interruptB
.address(addr[3:1]), // old name: address
.moduleEnableB(i2c_en_b), // old name: moduleEnableB
.writeEnableB(write_en_b), // old name: writeEnableB
.outputEnableB(read_en_b), // old name: outputEnableB
.byteEnableB(byte_en_7_0_b), // old name: byteEnableB
.clock(clk), // old name: clock
.resetB(~hard_rst_b), // old name: resetB
.disableB(~i2c_en_b), // removed
.sclOut(sclOut),
.sclIn(sclIn),
.sdaOut(sdaOut),
.sdaIn(sdaIn)
);
/****************************************************************************/
/* BDLC Module */
/****************************************************************************/
wire [7:0] dlc_do; // BDLC data output
wire [7:0] dlc_hiz; // Pad High Impedance (0=input, 1=output)
bdlc_1_0 BDLC (
.bdlc_int_t4i(int[4]), // old name: bdlc_int_t4i
.rdb_t2(data_rd_bdlc), // old name: rdb_t2
.dlc_do_t4(dlc_do),
.dlc_hiz_t4(dlc_hiz),
.dlc_ibe0_t2(), // removed
.dlc_ibe71_t2(), // removed
.dlc_pue10_t4(), // removed
.dlc_pue72_t4(), // removed
.dlc_rd10_t4(), // removed
.dlc_rd72_t4(), // removed
.bdlc_puerst_plug(), // removed
.dlcp_ind(dlcp_ind),
.vsc_en2drv(), // removed
.vsc_ab_t2(addr[3:0]), // old name: vsc_ab_t2[3:0]
.vsc_dlcsel_t3(~bdlc_en_b), // old name: vsc_dlcsel_t3
.vsc_reset_t4(hard_rst_b), // old name: vsc_reset_t4
.vsc_rw_t2(rw_t2), // old name: vsc_rw_t2
.vsc_scanmod(scanmod), // old name: vsc_scanmod
.vsc_smod_t2(test_mode), // old name: vsc_smod_t2
.vsc_stop_t2(stop_mode), // old name: vsc_stop_t2
.vsc_sz8_t2(byte_en_7_0_b), // old name: vsc_sz8_t2
.vsc_wait_t2(wait_mode), // old name: vsc_wait_t2
.vsc_wdb_t4(data_wr), // old name: vsc_wdb_t4
.vsc_clk41(clk) // old name: vsc_clk41
);
rdb_drv #(GBW) DLC_TRI ( .clk(clk), .en(dlc_hiz), .di(dlc_do), .do(dlc_do_t4) );
/****************************************************************************/
/* PWM Module */
/****************************************************************************/
wire [7:0] pwm_do; // PWM data output
wire [7:0] pwm_hiz; // Pad High Impedance (0=input, 1=output)
pwm_8b8c_1_0 PWM (
.rdb_t2(data_rd_pwm), // old name: rdb_t2
.pwm_do_t4(pwm_do),
.pwm_hiz_t4(pwm_hiz),
.pwm_ibe_t4(), // removed
.pwm_pue_t4(), // removed
.pwm_rd_t4(), // removed
.vsc_wdb_t4(data_wr), // old name: vsc_wdb_t4
.vsc_ab_t2(addr[5:0]), // old name: vsc_ab_t2
.vsc_clk41(clk), // old name: vsc_clk41
.vsc_rw_t2(rw_t2), // old name: vsc_rw_t2
.vsc_sz8_t2(byte_en_7_0_b), // old name:vsc_sz8_t2
.vsc_reset_t4(hard_rst_b), // old name: vsc_reset_t4
.vsc_stop_t2(stop_mode), // old name: vsc_stop_t2
.vsc_wait_t2(wait_mode), // old name: vsc_wait_t2
.vsc_smod_t2(test_mode), // old name: vsc_smod_t2
.vsc_bdmact_t2(freeze_mode), // old name: vsc_bdmact_t2
.vsc_pwmsel_t3(~pwm_en_b), // old name: vsc_pwmsel_t3
.vsc_scanmod(scanmod), // old name: vsc_scanmod
.pwmp_ind(pwmp_ind)
);
rdb_drv #(GBW) PWM_TRI ( .clk(clk), .en(pwm_hiz), .di(pwm_do), .do(pwm_do_t4) );
/****************************************************************************/
/* TIMER Module */
/****************************************************************************/
wire [7:0] tim_do; // TIMER data output
wire [7:0] tim_hiz; // Pad High Impedance (0=input, 1=output)
tim_16b8c_1_0 TIMER (
.rdb_t2(data_rd_tim), // old name: rdb_t2
.tim_int7_t4i(int[12]), // old name: tim_int7_t4i
.tim_int6_t4i(int[11]), // old name: tim_int6_t4i
.tim_int5_t4i(int[10]), // old name: tim_int5_t4i
.tim_int4_t4i(int[9]), // old name: tim_int4_t4i
.tim_int3_t4i(int[8]), // old name: tim_int3_t4i
.tim_int2_t4i(int[7]), // old name: tim_int2_t4i
.tim_int1_t4i(int[6]), // old name: tim_int1_t4i
.tim_int0_t4i(int[5]), // old name: tim_int0_t4i
.tim_paov_t4i(int[13), // old name: tim_paov_t4i
.tim_pa_t4i(int[14), // old name: tim_pa_t4i
.tim_ov_t4i(int[15), // old name: tim_ov_t4i
.tim_do_t4(tim_do),
.tim_hiz_t4(tim_hiz),
.tim_ibe_t2(), // removed
.tim_pue_t4(), // removed
.tim_rd_t4(), // removed
.vsc_wdb_t4(data_wr), // old name: vsc_wdb_t4
.vsc_ab_t2(addr), // old name: vsc_ab_t2
.timp_ind(timp_ind),
.vsc_rw_t2(rw_t2), // old name: vsc_rw_t2
.vsc_sz8_t2(byte_en_7_0_b), // old name: vsc_sz8_t2
.vsc_timsel_t3(~tim_en_b), // old name: vsc_timsel_t3
.vsc_smod_t2(test_mode), // old name: vsc_smod_t2
.vsc_bdmact_t2(freeze_mode), // old name: vsc_bdmact_t2
.vsc_wait_t2(wait_mode), // old name: vsc_wait_t2
.vsc_stop_t2(stop_mode), // old name: vsc_stop_t2
.vsc_reset_t4(hard_rst_b), // old name: vsc_reset_t4
.vsc_scanmod(scanmod), // old name: vsc_scanmod
.vsc_scane(vsc_scane),
.vsc_clk41(bus_clk), // old name: vsc_clk41
.vsc_busse(vsc_busse),
.tim_puerst_plug(), // removed
.vsc_en2drv() // removed
);
rdb_drv #(GBW) TIM_TRI ( .clk(clk), .en(tim_hiz), .di(tim_do), .do(tim_do_t4) );
/****************************************************************************/
/* CRG Module */
/****************************************************************************/
crg_1_0 #(GDBW, GABW) CRG1 (
.osc_clk(osc_clk),
.core_clk41(core_clk41),
.core_clk23(core_clk23),
.core_clk12(core_clk12),
.core_clk34(core_clk34),
.hard_rst_b(hard_rst_b),
.crg_en_b(crg_en_b),
.stop_mode(stop_mode),
.wait_mode(wait_mode)
);
/***************************************************************************************************
DATA MUX SECTION
// All of the module output data paths are multiplexed here.
***************************************************************************************************/
pif_data_mux MUX (
.sci1_en_b(sci1_en_b),
.sci2_en_b(sci2_en_b),
.spi_en_b(spi_en_b),
.i2c_en_b(i2c_en_b),
.bdlc_en_b(bdlc_en_b),
.pwm_en_b(pwm_en_b),
.tim_en_b(tim_en_b),
.data_rd_sci1(data_rd_sci1),
.data_rd_sci2(data_rd_sci2),
.data_rd_spi(data_rd_spi),
.data_rd_i2c(data_rd_i2c),
.data_rd_bdlc(data_rd_bdlc),
.data_rd_pwm(data_rd_pwm),
.data_rd_tim(data_rd_tim),
.data_rd(data_rd)
);
endmodule // pif_1_0
/*+FHDR**********************************************************************/
/* Copyright (c) 1997, Motorola. */
/* Motorola Confidential Proprietary */
/****************************************************************************/
// FILE NAME : pif_data_mux.v
// DEPARTMENT : MCU Design Center, Munich
// EMAIL : Andreas_Tuechler-R7906C@email.sps.mot.com
/****************************************************************************/
// version tag, generated by version control software
/****************************************************************************/
// Release history
// VERSION Date AUTHOR DESCRIPTION
// 1.0 09 Aug 1999 andreast initial version
//
/****************************************************************************/
// NAMES(TYPE) : pif_data_mux(module)
/****************************************************************************/
// KEYWORDS : data mux module
// PURPOSE : data multiplexing and module interface
/****************************************************************************/
// GLOBAL VARIABLES
// USED : none
// DEFINED : none
//
// DEPENDENCIES
// Verilog Version : XL 2.2.27
// Tools : Synopsys 1997.01
// Libraries : flex10k
// Other :
/*-FHDR**********************************************************************/
module pif_data_mux (
sci1_en_b,
sci2_en_b,
spi_en_b,
i2c_en_b,
bdlc_en_b,
pwm_en_b,
tim_en_b,
data_rd_sci1,
data_rd_sci2,
data_rd_spi,
data_rd_i2c,
data_rd_bdlc,
data_rd_pwm,
data_rd_tim,
data_rd
);
/****************************************************************************/
/* PORTS */
/****************************************************************************/
output [15:0] data_rd;
input sci1_en_b,
sci2_en_b,
spi_en_b,
i2c_en_b,
bdlc_en_b,
pwm_en_b,
tim_en_b;
input [15:0] data_rd_sci1,
data_rd_sci2,
data_rd_spi,
data_rd_bdlc,
data_rd_pwm,
data_rd_tim;
input [7:0] data_rd_i2c;
/****************************************************************************/
/* SIGNALS */
/****************************************************************************/
reg [15:0] dataMuxOut;
/****************************************************************************/
/* RTL */
/****************************************************************************/
always @( sci1_en_b or sci2_en_b or spi_en_b or i2c_en_b or bdlc_en_b or pwm_en_b or
tim_en_b or data_rd_sci1 or data_rd_sci2 or data_rd_spi or data_rd_i2c or
data_rd_bdlc or data_rd_pwm or data_rd_tim )
case ({sci1_en_b, sci2_en_b, spi_en_b, i2c_en_b, bdlc_en_b, pwm_en_b, tim_en_b})
7'b0111111 : dataMuxOut = data_rd_sci1;
7'b1011111 : dataMuxOut = data_rd_sci2;
7'b1101111 : dataMuxOut = data_rd_spi;
7'b1110111 : begin
dataMuxOut[7:0] = data_rd_i2c;
dataMuxOut[15:8]= 8'h0;
end
7'b1111011 : dataMuxOut = data_rd_bdlc;
7'b1111101 : dataMuxOut = data_rd_pwm;
7'b1111110 : dataMuxOut = data_rd_tim;
default : dataMuxOut = 8'h0;
endcase
assign data_rd = dataMuxOut;
endmodule // pif_data_mux
/*+FHDR**********************************************************************/
/* Copyright (c) 1997, Motorola. */
/* Motorola Confidential Proprietary */
/****************************************************************************/
// FILE NAME : rdb_drv.v
// DEPARTMENT : MCU Design Center, Munich
// EMAIL : Andreas_Tuechler-R7906C@email.sps.mot.com
/****************************************************************************/
// version tag, generated by version control software
/****************************************************************************/
// Release history
// VERSION Date AUTHOR DESCRIPTION
// 1.0 23 Aug 1999 andreast initial version
//
/****************************************************************************/
// NAMES(TYPE) : rdb_drv(module)
/****************************************************************************/
// KEYWORDS : tri-state buffer
// PURPOSE : creates bitwise enabled tri-state buffers
/****************************************************************************/
// GLOBAL VARIABLES
// USED : none
// DEFINED : none
//
// DEPENDENCIES
// Verilog Version : XL 2.2.27
// Tools : Synopsys 1997.01
// Libraries : flex10k
// Other :
/*-FHDR**********************************************************************/
module rdb_drv(clk, en, di, do);
/****************************************************************************/
/* PARAMETERS */
/****************************************************************************/
parameter GIBW = 8; // data bitwidth
/****************************************************************************/
/* PORTS */
/****************************************************************************/
input clk; // clock
input [GIBW-1:0] en; // enable
input [GIBW-1:0] di; // input Data Bus
output [GIBW-1:0] do; // output Data Bus
/****************************************************************************/
/* SIGNALS */
/****************************************************************************/
reg [GIBW-1:0] do; // output Data Bus
reg [GIBW-1:0] i; // variable index
/****************************************************************************/
/* RTL */
/****************************************************************************/
always @(en or clk or di)
begin
for ( i = 0; i < GIBW; i = i + 1 )
begin
if ( clk & en[i] )
do[i] <= di[i];
else
do[i] <= 1'bz;
end
end
endmodule // rdb_drv
/*+FHDR**********************************************************************/
/* Copyright (c) 1997, Motorola. */
/* Motorola Confidential Proprietary */
/****************************************************************************/
// FILE NAME : inv.v
// DEPARTMENT : MCU Design Center, Munich
// EMAIL : Andreas_Tuechler-R7906C@email.sps.mot.com
/****************************************************************************/
// version tag, generated by version control software
/****************************************************************************/
// Release history
// VERSION Date AUTHOR DESCRIPTION
// 1.0 18 Aug 1999 andreast initial version
//
/****************************************************************************/
// NAMES(TYPE) : inv(module)
/****************************************************************************/
// KEYWORDS : inverter module
// PURPOSE : invert bus signal
/****************************************************************************/
// GLOBAL VARIABLES
// USED : none
// DEFINED : none
//
// DEPENDENCIES
// Verilog Version : XL 2.2.27
// Tools : Synopsys 1997.01
// Libraries : flex10k
// Other :
/*-FHDR**********************************************************************/
module inv ( do, di );
/****************************************************************************/
/* PARAMETERS */
/****************************************************************************/
parameter GDBW = 16; // data bitwidth
/****************************************************************************/
/* PORTS */
/****************************************************************************/
output [GDBW-1:0] do; // output Data Bus
input [GDBW-1:0] di; // input Data Bus
/****************************************************************************/
/* RTL */
/****************************************************************************/
assign do = ~di;
endmodule // inv
-
FPGA3
- Wrapper module for FPGA3 (CAN0, CAN1).
/*+FHDR**********************************************************************/
/* Copyright (c) 1997, Motorola. */
/* Motorola Confidential Proprietary */
/****************************************************************************/
// FILE NAME : fpga3.v
// DEPARTMENT : MCU Design Center, Munich
// EMAIL : Andreas_Tuechler-R7906C@email.sps.mot.com
/****************************************************************************/
// version tag, generated by version control software
/****************************************************************************/
// Release history
// VERSION Date AUTHOR DESCRIPTION
// 1.3 15 Nov 1999 andreast updated IBBRIDGE and CAN modules
// 1.2 03 Nov 1999 andreast added ports for IP bus signals
// 1.0 24 Sep 1999 andreast initial version
//
/****************************************************************************/
// NAMES(TYPE) : fpga3_1_0(module)
/****************************************************************************/
// KEYWORDS : wrapper module for
// CAN0, CAN1 module
// PURPOSE : FPGA emulation
/****************************************************************************/
// GLOBAL VARIABLES
// USED : none
// DEFINED : none
//
// DEPENDENCIES
// Verilog Version : XL 2.2.27
// Tools : Synopsys 1997.01
// Libraries : flex10k
// Other :
//
// PARAMETERS
// PARAM NAME RANGE INIT TYPE : DESCRIPTION :
//
// core_smod_t2 I : Special mode enable :
// crg_wait_mode I : core WAIT enable :
// crg_stop_mode I : core STOP enable :
// crg_reset_ta4 I : core RESET enable :
// core_bdmact_t4 I : core BDM active enable :
// core_perisel_t2 I : core peripheral select enable :
// core_ab_t2 [15:0] I : core address bus :
// core_wdb_t4 [15:0] I : core write data bus :
// core_perisel_t2 I : core peripheral select enable:
// core_sz8_t2 I : core address size 8 or 16 bits:
// core_rw_t2 I : core read/write enable :
// crg_rti_int I : real time interrupt from crg:
// clk34 I : clock34 equal 1/2 of clk24 :
// crg_oscclk I : oscillator clock from CRG :
// ipb_addr [5:1] O : peripheral addr. reg. :
// ipb_rdata_L12 O : data read from peripheral :
// ipb_supervisor_access O : peripheral SUPERVISOR enable:
// ipg_hard_async_reset_b O : Asynchrous RESET :
// ipb_crg_en O : CRG module enable :
// ipb_ect_en O : TIMER module enable :
// ipb_sci0_en O : SCI0 module enable :
// ipb_spi_en O : SPI module enable :
// ipb_atd0_en O : ATD0 module enable :
// ipb_atd1_en O : ATD1 module enable :
// ipb_sci1_en O : SCI1 module enable :
// ipb_pwm_en O : PWM module enable :
// ipb_can0_en O : CAN0 module enable :
// ipb_can1_en O : CAN1 module enable :
// ipb_can2_en O : CAN2 module enable :
// ipb_can3_en O : CAN3 module enable :
// ipb_pim_en O : PORT module enable :
// ipb_iic_en O : IIC module enable :
// ipb_bdlc_en O : BDLC module enable :
// ipb_read O : read peripheral enable :
// ipb_write O : write peripheral enable :
// ipb_byte_en_15_8 O : high byte decoder enable :
// ipb_byte_en_7_0 O : low byte decoder enable :
// ipb_rtifff0i_t3 O : real time interrupt :
// : :
// -FHDR----------------------------------------------------------------------
module fpga3_1_0 (
/****************************************************************************/
/* STAR12 Bus Interface Signals */
/****************************************************************************/
// General Bus Signals (Classics)
core_wdb_t4,
core_ab_t2,
ipb_rdata_L12,
core_perisel_t2,
// Resets and Clocks
core_rw_t2,
core_sz8_t2,
crg_reset_ta4,
crg_stop_mode,
clk34,
crg_oscclk,
crg_wait_mode,
core_bdmact_t4,
core_smod_t2,
ipt_scan_mode,
// Interrupt Signals
ipb_ffxx_t3,
/****************************************************************************/
/* PORT signals */
/****************************************************************************/
ipp_rxcan_ind,
ipp_txcan_do,
ipp_port_en,
/****************************************************************************/
/* IP bus signals */
/****************************************************************************/
// IPbus-CLOCKS & RESETS
ipg_hard_async_reset_b,
// IPbus-PROTOCOL SIGNALS
ipb_addr,
ipb_byte_en_7_0,
ipb_byte_en_15_8,
ipb_read,
ipb_write,
ipb_supervisor_access,
ipb_rtifff0i_t3,
ipb_crg_offset,
// module enable signals
ipb_sci0_en,
ipb_sci1_en,
ipb_spi_en,
ipb_iic_en,
ipb_bdlc_en,
ipb_crg_en,
ipb_ect_en,
ipb_atd0_en,
ipb_pwm_en,
ipb_atd1_en,
ipb_can0_en,
ipb_can1_en,
ipb_can2_en,
ipb_can3_en,
ipb_pim_en
);
/****************************************************************************/
/* STAR12 Bus Interface Signals */
/****************************************************************************/
// General Bus Signals (Classics)
input [15:0] core_wdb_t4; // Write Data Bus
input [15:0] core_ab_t2; // Address Bus
output [15:0] ipb_rdata_L12; // Read Data Bus
input core_perisel_t2; // module select signal
// Resets and Modes
input core_rw_t2; // Read=1 / Write=0
input core_sz8_t2; // Size requested - sz8=1 (8-bit) / sz8=0 (16-bit)
input crg_reset_ta4; // Reset to main modules
input crg_stop_mode; // Stop to main modules
input clk34; // Bus rate clock 34
input crg_oscclk; // clock from crg module in FPGA2
input crg_wait_mode; // CPU wait signal
input core_bdmact_t4; // Background Debug
input core_smod_t2; // Special mode selected - used to activate "test" features
// Scan Test Signals
input ipt_scan_mode; // Scan mode
// Interrupt Signals
output [35:28] ipb_ffxx_t3; // CAN interrupts
/****************************************************************************/
/* PORTS Signals */
/****************************************************************************/
input [1:0] ipp_rxcan_ind; // CAN1, CAN2 input port
output [1:0] ipp_txcan_do; // CAN1, CAN2 output port
output [1:0] ipp_port_en; // CAN1, CAN2 output enable
/****************************************************************************/
/* IP bus signals */
/****************************************************************************/
// IPbus-CLOCKS & RESETS
output ipg_hard_async_reset_b;
// IPbus-PROTOCOL SIGNALS
output [5:1] ipb_addr;
output ipb_byte_en_7_0;
output ipb_byte_en_15_8;
output ipb_read;
output ipb_write;
output ipb_supervisor_access;
output ipb_rtifff0i_t3;
output ipb_crg_offset;
// module enable signals
output ipb_sci0_en;
output ipb_sci1_en;
output ipb_spi_en;
output ipb_iic_en;
output ipb_bdlc_en;
output ipb_crg_en;
output ipb_ect_en;
output ipb_atd0_en;
output ipb_atd1_en;
output ipb_pwm_en;
output ipb_can0_en;
output ipb_can1_en;
output ipb_can2_en;
output ipb_can3_en;
output ipb_pim_en;
/****************************************************************************/
/* SIGNALS */
/****************************************************************************/
// Outputs
wire ipi_can0_wu_int;
wire ipi_can0_er_int;
wire ipi_can0_rx_int;
wire ipi_can0_tx_int;
wire [15:0] ipb_can0_rdata;
wire ipi_can1_wu_int;
wire ipi_can1_er_int;
wire ipi_can1_rx_int;
wire ipi_can1_tx_int;
wire [15:0] ipb_can1_rdata;
wire can_clk_src0;
wire can_clk_src1;
wire ipg_core_clk0;
wire ipg_core_clk1;
wire ipg_cancore_clk0;
wire ipg_cancore_clk1;
wire ipg_core_clk_en0;
wire ipg_core_clk_en1;
wire ipg_cancore_clk_en0;
wire ipg_cancore_clk_en1;
// Inputs
wire ipg_hard_async_reset_b;
wire ipg_clk;
wire ipg_osc_clk;
wire ipb_clk0;
wire ipb_clk1;
wire ipg_can_clk0;
wire ipg_can_clk1;
wire [15:0] ipb_wdata;
wire [5:1] ipb_addr;
wire ipb_byte_en_7_0;
wire ipb_byte_en_15_8;
wire ipb_supervisor_access;
wire ipb_test_access;
wire ipg_stop;
wire ipg_wait;
wire ipt_scan_mode;
// instantiate gated clock cells
clkgate CAN_CORE_CLK0 (ipg_clk, ipg_core_clk_en0, ipg_core_clk0);
clkgate CAN_CANCORE_CLK0 (ipg_can_clk0, ipg_cancore_clk_en0, ipg_cancore_clk0);
clkgate CAN_CORE_CLK1 (ipg_clk, ipg_core_clk_en1, ipg_core_clk1);
clkgate CAN_CANCORE_CLK1 (ipg_can_clk1, ipg_cancore_clk_en1, ipg_cancore_clk1);
clkgate CAN_BUS_CLK0 (ipg_clk, ipb_can0_en, ipb_clk0);
clkgate CAN_BUS_CLK1 (ipg_clk, ipb_can1_en, ipb_clk1);
assign ipg_can_clk0 = can_clk_src0 ? ipg_clk : ipg_osc_clk;
assign ipg_can_clk1 = can_clk_src1 ? ipg_clk : ipg_osc_clk;
/****************************************************************************/
/* IPbridge */
/****************************************************************************/
s12_ipbi IPBRIDGE (
// General Bus Signals (Classics)
.core_wdb_t4 (core_wdb_t4), // Write Data Bus
.core_ab_t2 (core_ab_t2), // Address Bus
.ipb_rdata_L12 (ipb_rdata_L12), // Read Data Bus
.core_perisel_t2 (core_perisel_t2), // module select signal
// Resets and Modes
.core_rw_t2 (core_rw_t2), // Read=1 / Write=0
.core_sz8_t2 (core_sz8_t2), // Size requested - sz8=1 (8-bit) / sz8=0 (16-bit)
.crg_reset_ta4 (crg_reset_ta4), // Reset to main modules
.crg_stop_mode (crg_stop_mode), // Stop to main modules
.crg_wait_mode (crg_wait_mode), // CPU wait signal
.core_bdmact_t4 (core_bdmact_t4), // Background Debug Mode (BDM) active
.core_smod_t2 (core_smod_t2), // Special mode selected
// Scan Test Signals
.ipt_scan_mode (ipt_scan_mode), // Scan mode
// Interrupt Signals
.ipb_ffxx_t3 ({20'b0, ipb_ffxx_t3, 28'b0}), // interrupts
// IPbus-CLOCKS & RESETS
.ipg_clk (ipg_clk),
.clk34 (clk34),
.ipg_hard_async_reset_b (ipg_hard_async_reset_b),
.ipg_osc_clk (ipg_osc_clk),
.crg_oscclk (crg_oscclk),
// IPbus-PROTOCOL SIGNALS
.ipb_addr (ipb_addr),
.ipb_byte_en_7_0 (ipb_byte_en_7_0),
.ipb_byte_en_15_8 (ipb_byte_en_15_8),
.ipb_read (ipb_read),
.ipb_write (ipb_write),
.ipb_wdata (ipb_wdata),
.ipb_test_access (ipb_test_access),
.ipb_supervisor_access (ipb_supervisor_access),
.ipb_rtifff0i_t3 (ipb_rtifff0i_t3),
.ipb_crg_offset (ipb_crg_offset),
// IPbus-MODE SIGNALS
.ipg_freeze (ipg_freeze),
.ipg_stop (ipg_stop),
.ipg_wait (ipg_wait),
.ipg_doze (ipg_doze),
.ipg_soft_reset_b (ipg_soft_reset_b),
// module enable signals
.ipb_sci0_en (ipb_sci0_en),
.ipb_sci1_en (ipb_sci1_en),
.ipb_spi_en (ipb_spi_en),
.ipb_iic_en (ipb_iic_en),
.ipb_bdlc_en (ipb_bdlc_en),
.ipb_crg_en (ipb_crg_en),
.ipb_ect_en (ipb_ect_en),
.ipb_atd0_en (ipb_atd0_en),
.ipb_pwm_en (ipb_pwm_en ),
.ipb_atd1_en (ipb_atd1_en),
.ipb_can0_en (ipb_can0_en),
.ipb_can1_en (ipb_can1_en),
.ipb_can2_en (ipb_can2_en),
.ipb_can3_en (ipb_can3_en),
.ipb_pim_en (ipb_pim_en),
// IPbus-INTERRUPT SIGNALS
.ipi_ack_int (),
.ipi_rd_vector_int (),
.ipi_ect_ch0_int (),
.ipi_ect_ch1_int (),
.ipi_ect_ch2_int (),
.ipi_ect_ch3_int (),
.ipi_ect_ch4_int (),
.ipi_ect_ch5_int (),
.ipi_ect_ch6_int (),
.ipi_ect_ch7_int (),
.ipi_ect_ov_int (),
.ipi_ect_paov_int (),
.ipi_ect_pai_int (),
.ipi_spi_int (),
.ipi_sci0_int (),
.ipi_sci1_int (),
.ipi_atd0_int (),
.ipi_atd1_int (),
.ipi_pim_pj_int (),
.ipi_pim_ph_int (),
.ipi_ect_mcz_int (),
.ipi_ect_pbov_int (),
.ipi_crg_lck_int (),
.ipi_crg_scm_int (),
.ipi_bdlc_int (),
.ipi_iic_int (),
.ipi_eep_int (),
.ipi_fee_int (),
.ipi_can0_wu_int (ipi_can0_wu_int),
.ipi_can0_er_int (ipi_can0_er_int),
.ipi_can0_rx_int (ipi_can0_rx_int),
.ipi_can0_tx_int (ipi_can0_tx_int),
.ipi_can1_wu_int (ipi_can1_wu_int),
.ipi_can1_er_int (ipi_can1_er_int),
.ipi_can1_rx_int (ipi_can1_rx_int),
.ipi_can1_tx_int (ipi_can1_tx_int),
.ipi_can2_wu_int (),
.ipi_can2_er_int (),
.ipi_can2_rx_int (),
.ipi_can2_tx_int (),
.ipi_can3_wu_int (),
.ipi_can3_er_int (),
.ipi_can3_rx_int (),
.ipi_can3_tx_int (),
.crg_rti_int (),
// IPbus-DATA BUSSES
.ipb_crg_rdata (),
.ipb_ect_rdata (),
.ipb_atd0_rdata (),
.ipb_pwm_rdata (),
.ipb_sci0_rdata (),
.ipb_sci1_rdata (),
.ipb_spi_rdata (),
.ipb_iic_rdata (),
.ipb_bdlc_rdata (),
.ipb_atd1_rdata (),
.ipb_can0_rdata (ipb_can0_rdata),
.ipb_can1_rdata (ipb_can1_rdata),
.ipb_can2_rdata (),
.ipb_can3_rdata (),
.ipb_pim_rdata ()
);
/****************************************************************************/
/* MSCAN1 Module */
/****************************************************************************/
mscan MSCAN0 (
//output
.ipi_wakeup_int (ipi_can0_wu_int),
.ipi_err_int (ipi_can0_er_int),
.ipi_rx_int (ipi_can0_rx_int),
.ipi_tx_int (ipi_can0_tx_int),
.ipb_rdata (ipb_can0_rdata),
.can_clk_src (can_clk_src0),
.ipg_core_clk_en (ipg_core_clk_en0),
.ipg_cancore_clk_en (ipg_cancore_clk_en0),
.ipp_txcan_do (ipp_txcan_do[0]),
.ipp_port_en (ipp_port_en[0]),
//input
.ipg_hard_async_reset_b (ipg_hard_async_reset_b),
.ipg_clk (ipg_clk),
.ipb_clk (ipb_clk0),
.ipg_core_clk (ipg_core_clk0),
.ipg_can_clk (ipg_can_clk0),
.ipg_cancore_clk (ipg_cancore_clk0),
.ipb_wdata (ipb_wdata),
.ipb_addr (ipb_addr),
.ipb_byte_en_7_0 (ipb_byte_en_7_0),
.ipb_byte_en_15_8 (ipb_byte_en_15_8),
.ipb_module_en (ipb_can0_en),
.ipb_read_en (ipb_read),
.ipb_write_en (ipb_write),
.ipb_supervisor_access (ipb_supervisor_access),
.ipb_test_access (ipb_test_access),
.ipg_stop (ipg_stop),
.ipg_wait (ipg_wait),
.ipt_scan_mode (ipt_scan_mode),
.ipp_rxcan_ind (ipp_rxcan_ind[0])
);
/****************************************************************************/
/* MSCAN2 Module */
/****************************************************************************/
mscan MSCAN1 (
//output
.ipi_wakeup_int (ipi_can1_wu_int),
.ipi_err_int (ipi_can1_er_int),
.ipi_rx_int (ipi_can1_rx_int),
.ipi_tx_int (ipi_can1_tx_int),
.ipb_rdata (ipb_can1_rdata),
.can_clk_src (can_clk_src1),
.ipg_core_clk_en (ipg_core_clk_en1),
.ipg_cancore_clk_en (ipg_cancore_clk_en1),
.ipp_txcan_do (ipp_txcan_do[1]),
.ipp_port_en (ipp_port_en[1]),
//input
.ipg_hard_async_reset_b (ipg_hard_async_reset_b),
.ipg_clk (ipg_clk),
.ipb_clk (ipb_clk1),
.ipg_core_clk (ipg_core_clk1),
.ipg_can_clk (ipg_can_clk1),
.ipg_cancore_clk (ipg_cancore_clk1),
.ipb_wdata (ipb_wdata),
.ipb_addr (ipb_addr),
.ipb_byte_en_7_0 (ipb_byte_en_7_0),
.ipb_byte_en_15_8 (ipb_byte_en_15_8),
.ipb_module_en (ipb_can1_en),
.ipb_read_en (ipb_read),
.ipb_write_en (ipb_write),
.ipb_supervisor_access (ipb_supervisor_access),
.ipb_test_access (ipb_test_access),
.ipg_stop (ipg_stop),
.ipg_wait (ipg_wait),
.ipt_scan_mode (ipt_scan_mode),
.ipp_rxcan_ind (ipp_rxcan_ind[1])
);
endmodule // fpga3_1_0
-
FPGA4
- Wrapper module for FPGA4 (CAN2, CAN3).
/*+FHDR**********************************************************************/
/* Copyright (c) 1997, Motorola. */
/* Motorola Confidential Proprietary */
/****************************************************************************/
// FILE NAME : fpga4.v
// DEPARTMENT : MCU Design Center, Munich
// EMAIL : Andreas_Tuechler-R7906C@email.sps.mot.com
/****************************************************************************/
// version tag, generated by version control software
/****************************************************************************/
// Release history
// VERSION Date AUTHOR DESCRIPTION
// 1.1 17 Nov 1999 andreast updated IBBRIDGE and CAN modules
// 1.0 24 Sep 1999 andreast initial version
//
/****************************************************************************/
// NAMES(TYPE) : fpga4_1_0(module)
/****************************************************************************/
// KEYWORDS : wrapper module for
// can2, can3 module
// PURPOSE : FPGA emulation
/****************************************************************************/
// GLOBAL VARIABLES
// USED : none
// DEFINED : none
//
// DEPENDENCIES
// Verilog Version : XL 2.2.27
// Tools : Synopsys 1997.01
// Libraries : flex10k
// Other :
//
// PARAMETERS
// PARAM NAME RANGE INIT TYPE : DESCRIPTION :
//
// core_smod_t2 I : Special mode enable :
// crg_wait_mode I : core WAIT enable :
// crg_stop_mode I : core STOP enable :
// crg_reset_ta4 I : core RESET enable :
// core_bdmact_t4 I : core BDM active enable :
// core_perisel_t2 I : core peripheral select enable :
// core_ab_t2 [15:0] I : core address bus :
// core_wdb_t4 [15:0] I : core write data bus :
// core_perisel_t2 I : core peripheral select enable:
// core_sz8_t2 I : core address size 8 or 16 bits:
// core_rw_t2 I : core read/write enable :
// crg_rti_int I : real time interrupt from crg:
// clk34 I : clock34 equal 1/2 of clk24 :
// crg_oscclk I : oscillator clock from CRG :
// : :
// -FHDR----------------------------------------------------------------------
module fpga4_1_0 (
/****************************************************************************/
/* STAR12 Bus Interface Signals */
/****************************************************************************/
// General Bus Signals (Classics)
core_wdb_t4,
core_ab_t2,
ipb_rdata_L12,
core_perisel_t2,
// Resets and Clocks
core_rw_t2,
core_sz8_t2,
crg_reset_ta4,
crg_stop_mode,
clk34,
osc_clk,
crg_wait_mode,
core_bdmact_t4,
core_smod_t2,
ipt_scan_mode,
// Interrupt Signals
ipb_ffxx_t3,
/****************************************************************************/
/* PORT signals */
/****************************************************************************/
ipp_rxcan_ind,
ipp_txcan_do,
ipp_port_en
);
/****************************************************************************/
/* STAR12 Bus Interface Signals */
/****************************************************************************/
// General Bus Signals (Classics)
input [15:0] core_wdb_t4; // Write Data Bus
input [15:0] core_ab_t2; // Address Bus
output [15:0] ipb_rdata_L12; // Read Data Bus
input core_perisel_t2; // module select signal
// Resets and Modes
input core_rw_t2; // Read=1 / Write=0
input core_sz8_t2; // Size requested - sz8=1 (8-bit) / sz8=0 (16-bit)
input crg_reset_ta4; // Reset to main modules
input crg_stop_mode; // Stop to main modules
input clk34; // Bus rate clock 34
input osc_clk; // oscillator clock
input crg_wait_mode; // CPU wait signal
input core_bdmact_t4; // Background Debug
input core_smod_t2; // Special mode selected - used to activate "test" features
// Scan Test Signals
input ipt_scan_mode; // Scan mode
// Interrupt Signals
output [43:36] ipb_ffxx_t3; // CAN interrupts
/****************************************************************************/
/* PORTS Signals */
/****************************************************************************/
input [3:2] ipp_rxcan_ind; // can3, CAN2 input port
output [3:2] ipp_txcan_do; // can3, CAN2 output port
output [3:2] ipp_port_en; // can3, CAN2 output enable
/****************************************************************************/
/* SIGNALS */
/****************************************************************************/
// Outputs
wire ipi_can2_wu_int;
wire ipi_can2_er_int;
wire ipi_can2_rx_int;
wire ipi_can2_tx_int;
wire [15:0] ipb_can2_rdata;
wire ipi_can3_wu_int;
wire ipi_can3_er_int;
wire ipi_can3_rx_int;
wire ipi_can3_tx_int;
wire [15:0] ipb_can3_rdata;
wire can_clk_src2;
wire can_clk_src3;
wire ipg_core_clk2;
wire ipg_core_clk3;
wire ipg_cancore_clk2;
wire ipg_cancore_clk3;
wire ipg_core_clk_en2;
wire ipg_core_clk_en3;
wire ipg_cancore_clk_en2;
wire ipg_cancore_clk_en3;
// Inputs
wire ipg_hard_async_reset_b;
wire ipg_clk;
wire ipb_clk2;
wire ipb_clk3;
wire ipg_can_clk2;
wire ipg_can_clk3;
wire [15:0] ipb_wdata;
wire [5:1] ipb_addr;
wire ipb_byte_en_7_0;
wire ipb_byte_en_15_8;
wire ipb_supervisor_access;
wire ipb_test_access;
wire ipg_stop;
wire ipg_wait;
wire ipt_scan_mode;
// instantiate gated clock cells
clkgate CAN_CORE_CLK2 (ipg_clk, ipg_core_clk_en2, ipg_core_clk2);
clkgate CAN_CANCORE_CLK2 (ipg_can_clk2, ipg_cancore_clk_en2, ipg_cancore_clk2);
clkgate CAN_CORE_CLK3 (ipg_clk, ipg_core_clk_en3, ipg_core_clk3);
clkgate CAN_CANCORE_CLK3 (ipg_can_clk3, ipg_cancore_clk_en3, ipg_cancore_clk3);
clkgate CAN_BUS_CLK2 (ipg_clk, ipb_can2_en, ipb_clk2);
clkgate CAN_BUS_CLK3 (ipg_clk, ipb_can3_en, ipb_clk3);
assign ipg_can_clk2 = can_clk_src2 ? ipg_clk : osc_clk;
assign ipg_can_clk3 = can_clk_src3 ? ipg_clk : osc_clk;
/****************************************************************************/
/* IPbridge */
/****************************************************************************/
s12_ipbi IPBRIDGE (
// General Bus Signals (Classics)
.core_wdb_t4 (core_wdb_t4), // Write Data Bus
.core_ab_t2 (core_ab_t2), // Address Bus
.ipb_rdata_L12 (ipb_rdata_L12), // Read Data Bus
.core_perisel_t2 (core_perisel_t2), // module select signal
// Resets and Modes
.core_rw_t2 (core_rw_t2), // Read=1 / Write=0
.core_sz8_t2 (core_sz8_t2), // Size requested - sz8=1 (8-bit) / sz8=0 (16-bit)
.crg_reset_ta4 (crg_reset_ta4), // Reset to main modules
.crg_stop_mode (crg_stop_mode), // Stop to main modules
.crg_wait_mode (crg_wait_mode), // CPU wait signal
.core_bdmact_t4 (core_bdmact_t4), // Background Debug Mode (BDM) active
.core_smod_t2 (core_smod_t2), // Special mode selected
// Scan Test Signals
.ipt_scan_mode (ipt_scan_mode), // Scan mode
// Interrupt Signals
.ipb_ffxx_t3 ({40'b0, ipb_ffxx_t3, 8'b0}), // interrupts
// IPbus-CLOCKS & RESETS
.ipg_clk (ipg_clk),
.clk34 (clk34),
.ipg_hard_async_reset_b (ipg_hard_async_reset_b),
.ipg_osc_clk (ipg_osc_clk),
.crg_oscclk (osc_clk),
// IPbus-PROTOCOL SIGNALS
.ipb_addr (ipb_addr),
.ipb_byte_en_7_0 (ipb_byte_en_7_0),
.ipb_byte_en_15_8 (ipb_byte_en_15_8),
.ipb_read (ipb_read),
.ipb_write (ipb_write),
.ipb_wdata (ipb_wdata),
.ipb_test_access (ipb_test_access),
.ipb_supervisor_access (ipb_supervisor_access),
.ipb_rtifff0i_t3 (ipb_rtifff0i_t3),
.ipb_crg_offset (ipb_crg_offset),
// IPbus-MODE SIGNALS
.ipg_freeze (ipg_freeze),
.ipg_stop (ipg_stop),
.ipg_wait (ipg_wait),
.ipg_doze (ipg_doze),
.ipg_soft_reset_b (ipg_soft_reset_b),
// module enable signals
.ipb_sci0_en (),
.ipb_sci1_en (),
.ipb_spi_en (),
.ipb_iic_en (),
.ipb_bdlc_en (),
.ipb_crg_en (),
.ipb_ect_en (),
.ipb_atd0_en (),
.ipb_pwm_en (),
.ipb_atd1_en (),
.ipb_can0_en (),
.ipb_can1_en (),
.ipb_can2_en (ipb_can2_en),
.ipb_can3_en (ipb_can3_en),
.ipb_pim_en (),
// IPbus-INTERRUPT SIGNALS
.ipi_ack_int (),
.ipi_rd_vector_int (),
.ipi_ect_ch0_int (),
.ipi_ect_ch1_int (),
.ipi_ect_ch2_int (),
.ipi_ect_ch3_int (),
.ipi_ect_ch4_int (),
.ipi_ect_ch5_int (),
.ipi_ect_ch6_int (),
.ipi_ect_ch7_int (),
.ipi_ect_ov_int (),
.ipi_ect_paov_int (),
.ipi_ect_pai_int (),
.ipi_spi_int (),
.ipi_sci0_int (),
.ipi_sci1_int (),
.ipi_atd0_int (),
.ipi_atd1_int (),
.ipi_pim_pj_int (),
.ipi_pim_ph_int (),
.ipi_ect_mcz_int (),
.ipi_ect_pbov_int (),
.ipi_crg_lck_int (),
.ipi_crg_scm_int (),
.ipi_bdlc_int (),
.ipi_iic_int (),
.ipi_eep_int (),
.ipi_fee_int (),
.ipi_can0_wu_int (),
.ipi_can0_er_int (),
.ipi_can0_rx_int (),
.ipi_can0_tx_int (),
.ipi_can1_wu_int (),
.ipi_can1_er_int (),
.ipi_can1_rx_int (),
.ipi_can1_tx_int (),
.ipi_can2_wu_int (ipi_can2_wu_int),
.ipi_can2_er_int (ipi_can2_er_int),
.ipi_can2_rx_int (ipi_can2_rx_int),
.ipi_can2_tx_int (ipi_can2_tx_int),
.ipi_can3_wu_int (ipi_can3_wu_int),
.ipi_can3_er_int (ipi_can3_er_int),
.ipi_can3_rx_int (ipi_can3_rx_int),
.ipi_can3_tx_int (ipi_can3_tx_int),
.crg_rti_int (),
// IPbus-DATA BUSSES
.ipb_crg_rdata (),
.ipb_ect_rdata (),
.ipb_atd0_rdata (),
.ipb_pwm_rdata (),
.ipb_sci0_rdata (),
.ipb_sci1_rdata (),
.ipb_spi_rdata (),
.ipb_iic_rdata (),
.ipb_bdlc_rdata (),
.ipb_atd1_rdata (),
.ipb_can0_rdata (),
.ipb_can1_rdata (),
.ipb_can2_rdata (ipb_can2_rdata),
.ipb_can3_rdata (ipb_can3_rdata),
.ipb_pim_rdata ()
);
/****************************************************************************/
/* MScan3 Module */
/****************************************************************************/
mscan MSCAN2 (
//output
.ipi_wakeup_int (ipi_can2_wu_int),
.ipi_err_int (ipi_can2_er_int),
.ipi_rx_int (ipi_can2_rx_int),
.ipi_tx_int (ipi_can2_tx_int),
.ipb_rdata (ipb_can2_rdata),
.can_clk_src (can_clk_src2),
.ipg_core_clk_en (ipg_core_clk_en2),
.ipg_cancore_clk_en (ipg_cancore_clk_en2),
.ipp_txcan_do (ipp_txcan_do[2]),
.ipp_port_en (ipp_port_en[2]),
//input
.ipg_hard_async_reset_b (ipg_hard_async_reset_b),
.ipg_clk (ipg_clk),
.ipb_clk (ipb_clk2),
.ipg_core_clk (ipg_core_clk2),
.ipg_can_clk (ipg_can_clk2),
.ipg_cancore_clk (ipg_cancore_clk2),
.ipb_wdata (ipb_wdata),
.ipb_addr (ipb_addr),
.ipb_byte_en_7_0 (ipb_byte_en_7_0),
.ipb_byte_en_15_8 (ipb_byte_en_15_8),
.ipb_module_en (ipb_can2_en),
.ipb_read_en (ipb_read),
.ipb_write_en (ipb_write),
.ipb_supervisor_access (ipb_supervisor_access),
.ipb_test_access (ipb_test_access),
.ipg_stop (ipg_stop),
.ipg_wait (ipg_wait),
.ipt_scan_mode (ipt_scan_mode),
.ipp_rxcan_ind (ipp_rxcan_ind[2])
);
/****************************************************************************/
/* MSCAN2 Module */
/****************************************************************************/
mscan MSCAN3 (
//output
.ipi_wakeup_int (ipi_can3_wu_int),
.ipi_err_int (ipi_can3_er_int),
.ipi_rx_int (ipi_can3_rx_int),
.ipi_tx_int (ipi_can3_tx_int),
.ipb_rdata (ipb_can3_rdata),
.can_clk_src (can_clk_src3),
.ipg_core_clk_en (ipg_core_clk_en3),
.ipg_cancore_clk_en (ipg_cancore_clk_en1),
.ipp_txcan_do (ipp_txcan_do[3]),
.ipp_port_en (ipp_port_en[3]),
//input
.ipg_hard_async_reset_b (ipg_hard_async_reset_b),
.ipg_clk (ipg_clk),
.ipb_clk (ipb_clk3),
.ipg_core_clk (ipg_core_clk3),
.ipg_can_clk (ipg_can_clk3),
.ipg_cancore_clk (ipg_cancore_clk3),
.ipb_wdata (ipb_wdata),
.ipb_addr (ipb_addr),
.ipb_byte_en_7_0 (ipb_byte_en_7_0),
.ipb_byte_en_15_8 (ipb_byte_en_15_8),
.ipb_module_en (ipb_can3_en),
.ipb_read_en (ipb_read),
.ipb_write_en (ipb_write),
.ipb_supervisor_access (ipb_supervisor_access),
.ipb_test_access (ipb_test_access),
.ipg_stop (ipg_stop),
.ipg_wait (ipg_wait),
.ipt_scan_mode (ipt_scan_mode),
.ipp_rxcan_ind (ipp_rxcan_ind[3])
);
endmodule // fpga4_1_0
-
FPGA5
- Wrapper module for FPGA5 (SRAM Interface).
/*+FHDR**********************************************************************/
/* Copyright (c) 1997, Motorola. */
/* Motorola Confidential Proprietary */
/****************************************************************************/
// FILE NAME : fpga5.v
// DEPARTMENT : MCU Design Center, Munich
// EMAIL : Andreas_Tuechler-R7906C@email.sps.mot.com
/****************************************************************************/
// version tag, generated by version control software
/****************************************************************************/
// Release history
// VERSION Date AUTHOR DESCRIPTION
// 1.0 25 Aug 1999 andreast initial version
//
/****************************************************************************/
// NAMES(TYPE) : fpga5(module)
/****************************************************************************/
// KEYWORDS : memory emulation module
// PURPOSE : emulates EEPROM, Flash and RAM using one SRAM device
/****************************************************************************/
// GLOBAL VARIABLES
// USED : none
// DEFINED : none
//
// DEPENDENCIES
// Verilog Version : XL 2.2.27
// Tools : Synopsys 1997.01
// Libraries : flex10k
// Other :
/*-FHDR**********************************************************************/
module fpga5_1_0
(
/****************************************************************************/
/* STAR12 Bus Interface Signals */
/****************************************************************************/
// General Bus Signals (Classics)
writdb,
addbus,
readdb,
perisel,
// Resets and Clocks
readwrit,
size8,
reset,
stopmode,
clk41,
clk34,
waitmode,
bdmack,
modesel,
smode,
// Scan Test Signals
scanmode,
// Interrupt Signals
ffxx,
// Selects
eearsel,
eeregsel,
feearsel,
feeresel,
ramarsel,
ramresel,
/****************************************************************************/
/* SRAM CTL Signals */
/****************************************************************************/
// Low Byte SRAM Signals
A_H_L,
D_L,
CEN_L,
OEN_L,
WEN_L,
Q_L,
// High Byte SRAM Signals
D_H,
CEN_H,
OEN_H,
WEN_H,
Q_H
);
/****************************************************************************/
/* PARAMETERS */
/****************************************************************************/
parameter GDBW = 16; // data bitwidth
parameter GABW = 16; // address bitwidth
parameter GIBW = 19; // interrupt bitwidth
parameter GBW = 8; // 8 bit data bitwidth
parameter GDBW2 = GDBW/2; // data bitwidth low/high Byte
parameter GFEAD = 1024; // Flash Address Offset in RAM
parameter GEEAD = 512; // EEPROM Address Offset in RAM
parameter GRAMAD = 0; // RAM Starting Address
/****************************************************************************/
/* STAR12 Bus Interface Signals */
/****************************************************************************/
// General Bus Signals (Classics)
input [GDBW-1:0] writdb; // Write Data Bus
input [GABW-1:0] addbus; // Address Bus
output [GDBW-1:0] readdb; // Read Data Bus
input perisel; // module select signal
// Resets and Modes
input readwrit; // Read=1 / Write=0
input size8; // Size requested - sz8=1 (8-bit) / sz8=0 (16-bit)
input reset; // Reset to main modules
input stopmode; // Stop to main modules
input clk41; // Bus rate clock 41
input clk34; // Bus rate clock 34
input waitmode; // CPU wait signal
input bdmack; // Background Debug Mode (BDM) active
input modesel;
input smode; // Special mode selected - used to activate "test" features
// Scan Test Signals
input scanmode; // Scan mode
// Interrupt Signals
output [GIBW-1:0] ffxx;
// Selects
input eearsel; // EEPROM array select for interfacing to EEPROM array -if needed
input eeregsel; // EEPROM register select for interfacing to registers inside module - if needed
input feearsel; // Flash memory array select - if needed
input feeresel; // Flash memory register select - if needed
input ramarsel; // RAM select for interfacing to RAM array - if needed
input ramresel; // RAM select for interfacing to RAM register - if needed
/****************************************************************************/
/* SRAM CTL Signals */
/****************************************************************************/
// Low Byte SRAM Signals
output [GABW-1:0] A_H_L; // SRAM Address bus
output [GDBW2-1:0] D_L; // SRAM Data in
output CEN_L; // SRAM Chip Enable
output OEN_L; // SRAM Output Enable
output WEN_L; // SRAM Write Enable
input [GDBW2-1:0] Q_L; // SRAM Data out
// High Byte SRAM Signals
output [GDBW2-1:0] D_H; // SRAM Data in
output CEN_H; // SRAM Chip Enable
output OEN_H; // SRAM Output Enable
output WEN_H; // SRAM Write Enable
input [GDBW2-1:0] Q_H; // SRAM Data out
/****************************************************************************/
/* SIGNALS */
/****************************************************************************/
wire mem_en; // memory enable
reg [GABW-1:0] A_L; // SRAM Address bus, low byte
/****************************************************************************/
/* RTL */
/****************************************************************************/
/****************************************************************************/
/* IPbridge */
/****************************************************************************/
ipbridge_1_0 IP_BRIDGE
(
// General Bus Signals (Classics)
.core_wdb_t4(writdb),
.core_ab_t2(addbus),
.rdb_t2(readdb),
.core_perisel_t2(perisel),
// Resets and Clocks
.core_rw_t2(readwrit),
.core_sz8_t2(size8),
.core_rst_t3(reset),
.core_stop_t2(stopmode),
.core_clk41(clk41),
.core_clk34(clk34),
.core_wait_t2(waitmode),
.core_bdmact_t2(bdmack),
.core_modsel_t3(modesel),
.core_smod_t2(smode),
// Scan Test Signals
.core_scanmod_t2(scanmode),
// Interrupt Signals
.ffxx(ffxx),
// IPbus-CLOCKS & RESETS
.clk(clk),
.bus_clk(),
.clk34(),
.hard_rst_b(),
// IPbus-DATA BUSSES
.data_wr(),
.sci1_data_rd(),
.sci2_data_rd(),
.spi_data_rd(),
.i2c_data_rd(),
.bdlc_data_rd(),
.pwm_data_rd(),
.tim_data_rd(),
.crg_data_rd(),
.kwu_data_rd(),
.pim_data_rd(),
.can1_data_rd(),
.can2_data_rd(),
.can3_data_rd(),
.can4_data_rd(),
// IPbus-PROTOCOL SIGNALS
.addr(addbus),
.byte_en_7_0_b(),
.byte_en_15_8_b(),
.read_en_b(),
.write_en_b(),
// module enable signals
.sci1_en_b(),
.sci2_en_b(),
.spi_en_b(),
.i2c_en_b(),
.bdlc_en_b(),
.pwm_en_b(),
.tim_en_b(),
.crg_en_b(),
.kwu_en_b(),
.pim_en_b(),
.can1_en_b(),
.can2_en_b(),
.can3_en_b(),
.can4_en_b(),
// IPbus-MODE SIGNALS
.freeze_mode(),
.stop_mode(),
.wait_mode(),
.smodT4(),
.scanmod(),
// IPbus-INTERRUPT SIGNALS
.int_b()
);
assign mem_en = eearsel | feearsel | ramarsel;
// Low Byte SRAM Signals
assign CEN_L = mem_en & size8; // SRAM Chip Enable low byte
assign OEN_L = mem_en & size8 & readwrit; // SRAM output Enable low byte
assign WEN_L = mem_en & size8 & ~readwrit; // SRAM Write Enable low byte
// High Byte SRAM Signals
assign CEN_H = mem_en & ~size8; // SRAM Chip Enable high byte
assign OEN_H = mem_en & ~size8 & readwrit; // SRAM output Enable high byte
assign WEN_H = mem_en & ~size8 & ~readwrit; // SRAM Write Enable high byte
// STAR-Bus Signals
// register joint EEPROM, Flash, RAM Read Data Bus
Reg #(GDBW) RDB_REG (
.c(clk34),
.rb(reset),
.en(mem_en),
.d({Q_H, Q_L}),
.q(readdb)
);
// register joint EEPROM, Flash, RAM Write Data Bus
Reg #(GDBW) WDB_REG (
.c(clk34),
.rb(reset),
.en(mem_en),
.d(writdb),
.q({D_H, D_L})
);
// redirect data to appropriate upper memory area in RAM
always @( eearsel or feearsel or ramarsel or
A_L or addbus )
begin
// default values
A_L = A_L;
case ({eearsel, feearsel, ramarsel})
3'b100 : A_L = addbus + GEEAD;
3'b010 : A_L = addbus + GFEAD;
3'b001 : A_L = addbus + GRAMAD;
endcase
end
assign A_H_L = A_L;
endmodule // fpga5_1_0
/*+FHDR**********************************************************************/
/* Copyright (c) 1997, Motorola. */
/* Motorola Confidential Proprietary */
/****************************************************************************/
// FILE NAME : inv.v
// DEPARTMENT : MCU Design Center, Munich
// EMAIL : Andreas_Tuechler-R7906C@email.sps.mot.com
/****************************************************************************/
// version tag, generated by version control software
/****************************************************************************/
// Release history
// VERSION Date AUTHOR DESCRIPTION
// 1.0 18 Aug 1999 andreast initial version
//
/****************************************************************************/
// NAMES(TYPE) : inv(module)
/****************************************************************************/
// KEYWORDS : inverter module
// PURPOSE : invert bus signal
/****************************************************************************/
// GLOBAL VARIABLES
// USED : none
// DEFINED : none
//
// DEPENDENCIES
// Verilog Version : XL 2.2.27
// Tools : Synopsys 1997.01
// Libraries : flex10k
// Other :
/*-FHDR**********************************************************************/
module inv ( do, di );
/****************************************************************************/
/* PARAMETERS */
/****************************************************************************/
parameter GDBW = 16; // data bitwidth
/****************************************************************************/
/* PORTS */
/****************************************************************************/
output [GDBW-1:0] do; // output Data Bus
input [GDBW-1:0] di; // input Data Bus
/****************************************************************************/
/* RTL */
/****************************************************************************/
assign do = ~di;
endmodule // inv
/*+FHDR**********************************************************************/
/* Copyright (c) 1997, Motorola. */
/* Motorola Confidential Proprietary */
/****************************************************************************/
// FILE NAME : Reg.v
// DEPARTMENT : MCU Design Center, Munich
// EMAIL : Andreas_Tuechler-R7906C@email.sps.mot.com
/****************************************************************************/
// version tag, generated by version control software
/****************************************************************************/
// Release history
// VERSION Date AUTHOR DESCRIPTION
// 1.0 19 Aug 1999 andreast initial version
//
/****************************************************************************/
// NAMES(TYPE) : Reg(module)
/****************************************************************************/
// KEYWORDS : creates a register
// PURPOSE : registering signals
/****************************************************************************/
// GLOBAL VARIABLES
// USED : none
// DEFINED : none
//
// DEPENDENCIES
// Verilog Version : XL 2.2.27
// Tools : Synopsys 1997.01
// Libraries : flex10k
// Other :
/*-FHDR**********************************************************************/
module Reg (c, rb, en, d, q);
/****************************************************************************/
/* PARAMETERS */
/****************************************************************************/
parameter GBW = 8; // data bitwidth
/****************************************************************************/
/* PORTS */
/****************************************************************************/
input c, rb, en;
output [GBW-1:0] q; // output Data Bus
input [GBW-1:0] d; // input Data Bus
/****************************************************************************/
/* SIGNALS */
/****************************************************************************/
wire [GBW-1:0] d_en;
reg [GBW-1:0] q;
/****************************************************************************/
/* RTL */
/****************************************************************************/
always @( posedge c or negedge rb )
begin
if ( !rb )
q <= 1'b0;
else
q <= d_en;
end
assign d_en = en ? d : q; // hold value if not enabled
endmodule // Reg
/*+FHDR**********************************************************************/
/* Copyright (c) 1997, Motorola. */
/* Motorola Confidential Proprietary */
/****************************************************************************/
// FILE NAME : Reg.v
// DEPARTMENT : MCU Design Center, Munich
// EMAIL : Andreas_Tuechler-R7906C@email.sps.mot.com
/****************************************************************************/
// version tag, generated by version control software
/****************************************************************************/
// Release history
// VERSION Date AUTHOR DESCRIPTION
// 1.0 19 Aug 1999 andreast initial version
//
/****************************************************************************/
// NAMES(TYPE) : Reg(module)
/****************************************************************************/
// KEYWORDS : creates a register
// PURPOSE : registering signals
/****************************************************************************/
// GLOBAL VARIABLES
// USED : none
// DEFINED : none
//
// DEPENDENCIES
// Verilog Version : XL 2.2.27
// Tools : Synopsys 1997.01
// Libraries : flex10k
// Other :
/*-FHDR**********************************************************************/
module latch ( di, en, do );
/****************************************************************************/
/* PARAMETERS */
/****************************************************************************/
parameter GBW = 8; // data bitwidth
/****************************************************************************/
/* PORTS */
/****************************************************************************/
input en;
output [GBW-1:0] do; // output Data Bus
input [GBW-1:0] di; // input Data Bus
/****************************************************************************/
/* SIGNALS */
/****************************************************************************/
reg [GBW-1:0] do;
/****************************************************************************/
/* RTL */
/****************************************************************************/
always @( en or di )
begin
if ( en )
begin
do = di;
end
end
endmodule // latch
-
Table 1 Altera Fitting Report summary
|
Altera Fitting Statistics |
| Module |
Clock |
Frequency |
ALTERA device |
Total I/O pins used: |
Total logic cells used: |
| CPU |
115.8ns |
8.63MHz |
FLEX10K100 |
46/141 ( 53%) |
4655/4992 ( 93%) |
| FSC |
|
|
FLEX10K130 |
191/407 ( 46%) |
1230/6656 ( 18%) |
| VSC |
|
|
FLEX10K130 |
369/407 ( 90%) |
1499/6656 ( 22%) |
| CORE |
123.5ns |
8.09MHz |
EPF10K200EQC599 |
299/464 ( 64%) |
6988/9984 ( 69%) |
| FPGA1 |
|
8.12MHz |
EPF10K200EQC240 |
164/176 ( 93%) |
6993/9984 ( 70%) |
| FPGA2 |
|
|
EPF10K130EQC240 |
117/180 ( 65%) |
3257/6656 ( 48%) |
| FPGA3 |
|
|
EPF10K130EQC240 |
68/180 ( 37%) |
( %) |
| FPGA4 |
|
|
EPF10K130EQC240 |
68/180 ( 37%) |
( %) |
| FPGA5 |
|
|
EPF10K30EQC208-1 |
124/141 ( 87%) |
120/1728 ( 6%) |
| SCI |
51.8ns |
19.30MHz |
FLEX10K30 |
56/96 ( 58%) |
375/1728 ( 21%) |
| SPI |
54.8ns |
18.24MHz |
FLEX10K30 |
67/96 ( 69%) |
184/1728 ( 10%) |
| I2C |
12.4ns |
80.64MHz |
FLEX10K30 |
25/96 ( 26%) |
342/1728 ( 19%) |
| BDLC |
|
|
FLEX10K30 |
71/96 ( 73%) |
684/1728 ( 39%) |
| PWM |
|
|
FLEX10K30 |
70/96 ( 72%) |
1686/1728 ( 97%) |
| TIMER |
|
|
EPF10K30ETC144 |
82/96 ( 95%) |
1033/1728 ( 59%) |
| CRG |
|
(Preliminary) |
EPF10K30ETC144 |
7/96 ( 3%) |
4/1728 ( 7%) |
| KWU |
|
|
EPF10K30ETC144 |
90/96 ( 93%) |
225/1728 ( 13%) |
| MSCAN |
|
|
FLEX10K100 |
87/141 ( 61%) |
2996/4992 ( 60%) |
| PIM |
|
(Preliminary) |
EPF10K30EFC484 |
203/214 ( 98%) |
140/1728 ( 8%) |
| SRAM_INT |
|
(Preliminary) |
EPF10K30ETC144 |
84/1728 ( 98%) |
61/1728 ( 3%) |
| IPbridge |
4.0ns |
250 MHz |
EPF10K130EFC672 |
368/407 ( 90%) |
265/6656 ( 3%) |
SCI+SPI+BDLC+
PWM+I2C |
|
|
EPF10K100EBC356 |
230/268 ( 85%) |
3309/4992 ( 66%) |
IPbus+SCI+SPI+
I2C+BDLC+PWM |
|
|
EPF10K100EQC240 |
167/183 ( 91%) |
3268/4992 ( 65%) |
IPbus+SCI+SPI+
I2C+BDLC+
PWM+TIMER |
|
|
EPF10K100EQC240 |
143/183 ( 77%) |
4643/4992 ( 93%) |
STAR12<=>IPbus,
RAM CTL |
4.0ns |
250MHz |
EPF10K30EFC484 |
213/214 ( 99%) |
145/1728 ( 8%) |