Appendix B

Generic Synthesis Scripts

Global Setup

The following script initializes Synopsys Design Compiler for FPGA synthesis (adapted from Synopsys design specific stuff).

/***********************************/
/* Global Setup Info for Synthesis */
/***********************************/

/* Design Header Info */
/* ------------------ */
designer = "Andreas Tuechler";
company  = "MOTOROLA";

/* ----------------------------------------------*/
/* Define module-independent directory structure */
/* ----------------------------------------------*/

/* Top-level design path */
DESIGN_TOP = PROJECTD + "/" + MODULE;

/* Search path to PRIMITIVES */
PRIMD = PROJECTD + "/PRIMITIVES";

/* Search path to RTL models */
MODELD = DESIGN_TOP + "/rtl_v";

/* Search path to scripts */
SCRIPTD = DESIGN_TOP + "/scripts";

/* List of verilog design files to be read */
SYNMODEL = SCRIPTD + "/" + MODULE + "_files.list"

/* List of verilog models/blocks to be compiled */
DESIGN = SCRIPTD + "/" + MODULE + "_design.list"

/* List of verilog models/blocks to be compiled */
RMPORTS = SCRIPTD + "/" + MODULE + "_remove_port.list"

/* Synopsys working path */
TEMPD = DESIGN_TOP + "/tool_data/FPGAsynopsys";

/* Search path to log files */
LOGD = DESIGN_TOP + "/logfiles";

/* technology */
technology = flex10k;

/* technology library */
TLIB = {technology + ".db"};

/* symbolic library */
SLIB = {altera.sdb};

/* library path */
LIB_PATH = "/tool/altera/synopsys/library/alt_syn/" + technology + "/lib";

/*specific directories */
DIR_LIST = {"reports", "tool_data/FPGAaltera", "tool_data/FPGAsynopsys", "tool_data/FPGAsynopsys/VERSION_1", "tool_data/FPGAsynopsys/VERSION_2", "tool_data/FPGAaltera/VERSION_1", "tool_data/FPGAaltera/VERSION_2" };


cd DESIGN_TOP
sh mkdir "tool_data/FPGAsynopsys/VERSION_1";
sh mkdir "tool_data/FPGAaltera/VERSION_1";

/* ------------------ */
/* Design Maintenance */
/* ------------------ */
define_design_lib WORK -path TEMPD
command_log_file      = LOGD + "/command.log"
view_log_file         = LOGD + "/view.log"
view_command_log_file = LOGD + "/view_command.log"


/* ------------- */
/* Library setup */
/* ------------- */
search_path    = {". ", std_lib, GLOBAL_VERILOG, LIB_PATH, MODELD, PRIMD, SCRIPTD};
target_library = TLIB; 
symbol_library = SLIB;
link_library   = TLIB;  

 
/* bb altera -path /tool/altera/synopsys/library/alt_mf/lib */

/* ---------------------- */
/* Design Compiler Select */
define_design_lib DW_FLEX10K -path /tool/altera/synopsys/library/alt_syn/flex10k/lib/dw_flex10k;
/* define_design_lib DW_FLEX10K_FPGA -path /tool/altera/synopsys/library/alt_syn/flex10k/lib/dw_flex10k_fpga */
/* ---------------------- */

/* DESIGN Specific Stuff */
/* --------------------- */
compile_preserve_subdesign_interfaces = "TRUE";
hdlout_internal_busses		      = "TRUE";
verilogout_no_tri                     = "TRUE";
verilogout_show_unconnected_pins      = "TRUE";
bus_dimension_separator_style 	      = "][";
bus_naming_style		      = "%s[%d]";	
bus_inference_style                   = "%s[%d]";

set_fix_multiple_port_nets    -all;
net_name_layer.visible        = "true";
pin_name_layer.visible        = "true";
db2sge_display_instance_names = "true";
db2sge_display_pin_names      = "true";
db2sge_display_symbol_names   = "true";


/* EDIF Netlisting */
/* =============== */
edifout_netlist_only                    = "true";
edifout_power_and_ground_representation = "net";
edifout_power_net_name                  = "VDD";
edifout_ground_net_name                 = "GND";
edifout_external                        = "true";
edifout_ground_pin_name                 = "OUT";
edifout_instantiate_ports               = "FALSE";

edifout_write_properties_list = { DPLD_IPLEVEL, DPLD_OPSLEW, DPLD_OPLEVEL, DPLD_OPDRIVE, PULLDOWN, PULLUP, DPLD_PAD_PLACE, DPLD_PUP }

edifin_power_net_name  = "VDD";
edifin_ground_net_name = "GND";

/* --------------- */
/* ====> for non-bus output */
/* edifout_no_array = "TRUE"; */
/* ====> for bus output */
edifout_no_array    = "FALSE" 
/* --------------- */

/* Verilog */
/* ======= */
hdlin_enable_vpp			= "TRUE"; /*Enable Verilog Preprocesor*/
hdlin_enable_analysis_info		= "TRUE"; /*generation of RTL_Analyzer analysis information.
verilogout_no_tri                       = "TRUE";
verilogout_show_unconnected_pins	= "TRUE";
verilogout_single_bit                   = "FALSE"; /*Keep buses*/

/* Utilities */
/* ========= */
gen_show_created_symbols   = "FALSE";
text_editor_command        = "xterm -fn 8x13 -e nedit %s &";
text_print_command         = "enscript -2rG -Plw3";
view_command_win_max_lines = 200000;

/* Alias */
/* ===== */
alias act current_design;
alias rm_all remove_design -all;

/* Actual Design Version */
VERSIOND = "_1";

/*  Check data/paths */
/* ----------------- */
include PROJECTD + "/scripts/check_vars.scr" > reports + "/" + DESIGN_TOP_PREROUTE + "_check_vars.rpt"
This script runs first and checks all defined variables and directories for existens.
/*RCS info at the end of the file*/
/*-----------------------------------*/
/* Check for Variable existence here */
/*-----------------------------------*/
echo ""
list DESIGN_TOP > /deappendix/appa.htm1v/null
if (dc_shell_status == 0) { 
   echo "Error variable DESIGN_TOP not set, quitting"
   quit
}appendix/appa.htm1

list DESIGN_TOP_PREROUTE > /dev/null
if (dc_shell_status == 0) { 
   DESIGN_TOP_PREROUTE = DESIGN_TOP
}
 
list PRIMD > /dev/null
if (dc_shell_status == 0) {
   echo "Error variable PRIMD (Search path to PRIMITIVES) not set, quitting"
   quit
}

list TLIB > /dev/null
if (dc_shell_status == 0) {
   echo "Error variable TLIB not set, quitting"
   quit
}

list SLIB > /dev/null
if (dc_shell_status == 0) {
   echo "Error variable SLIB not set, quitting"
   quit
}

list LIB_PATH > /dev/null
if (dc_shell_status == 0) { 
   echo "Error variable LIB_PATH not set, quitting"
   quit
} 

/*-----------------------------------------------------*/
/* Check for directory existence here */
/*-----------------------------------------------------*/
list SYNMODEL > /dev/null
if (dc_shell_status == 0)
{ 
	echo "Error variable SYMODEL not set, quitting"
	quit
}

sh test -f SYNMODEL 
if (dc_shell_status != 0)
{
	echo "Error file SYNMODEL not found, quitting"
	quit
}

list DESIGN > /dev/null
if (dc_shell_status == 0)
{ 
	echo "Error variable DESIGN not set, quitting"
	quit
}

sh test -f DESIGN 
if (dc_shell_status != 0)
{
	echo "Error file DESIGN not found, quitting"
	quit
}

list RMPORTS > /dev/null
if (dc_shell_status == 0)
{ 
	echo "Error variable RMPORTS not set, quitting"
	quit
}

sh test -f RMPORTS 
if (dc_shell_status != 0)
{
	echo "Error file: RMPORTS not found, quitting"
	list RMPORTS;
	echo "not found, quitting"
	quit
}

list MODELD > /dev/null
if (dc_shell_status == 0)
{ 
	echo "Error variable MODELD not set, quitting"
	quit
} 

foreach (mod, MODELD)
{
        sh test -d mod
        if (dc_shell_status != 0)
        {
                echo "Error directory MODELD not found, quitting"
                list mod
                quit
        } 
}

list SCRIPTD > /dev/null
if (dc_shell_status != 0)
{
	echo "Adding SCRIPTD to end of search_path list";
}

/* check directories */
foreach (dir, DIR_LIST)
{
        sh test -d dir
        if (dc_shell_status != 0)
        {
		echo "Info: directory not found, creating directory";
		list dir;
        } 

       	sh test -d dir;
	if (dc_shell_status != 0)
	{
		echo "Info: unable to create directory";
		list dir;
	}
}
Analyze, Elaborate

The following scripts analyzes and elarorates all verilog modules listed in file SYNMODEL.

/* ------------- */
/* A N A L Y Z E */
/* ------------- */
sh test -f SYNMODEL
if (dc_shell_status == 0)
{
   remove_variable vlist > /dev/null
   vlist = execute(-s, sh echo `cat SYNMODEL `)
}

analyze -f verilog -lib WORK vlist > reports + "/" + DESIGN_TOP_PREROUTE + "_anal.rpt"
if (dc_shell_status == 0)
{
        echo "Error - Analyze Failed"
        quit
}

/* ----------------- */
/* E L A B O R A T E */
/* ----------------- */
sh test -f DESIGN
if (dc_shell_status == 0)
{
   remove_variable dlist > /dev/null
   dlist = execute(-s, sh echo `cat DESIGN `)
}

foreach (dsn, dlist)
{
	elaborate dsn -arch "verilog" -lib WORK -update  > reports + "/" + DESIGN_TOP_PREROUTE + "_elab.rpt"

        if (dc_shell_status == 0)
        {
                list dsn
                echo "Error: specified DESIGN not found"
        } 
}
Read
The following script reads in verilog files. It should be used for modules that have already been analyzed.
/* ------- */
/* R E A D */
/* ------- */
sh test -f SYNMODEL
if (dc_shell_status == 0)
{
   remove_variable vlist > /dev/null
   vlist = execute(-s, sh echo `cat SYNMODEL `)
}

read vlist;

if (dc_shell_status == 0)
{
        echo "Error - READ Failed"
        quit
}
Compile
This script performs a standard compilation.
/* -------------------- */
/* Schematic Generation */
/* -------------------- */
sh test -f DESIGN
if (dc_shell_status == 0)
{
   remove_variable dlist > /dev/null
   dlist = execute(-s, sh echo `cat DESIGN `)
}

foreach (dsn, dlist)
{
	current_design dsn

	uniquify

	compile  -map_effort low

	set_dont_touch dsn

        if (dc_shell_status == 0)
        {
                echo "Error: specified DESIGN not found, quitting"
                list dsn
                quit
        } 
}
Run standard compilation
This script calls other dedicated scripts used for compilation of Barracuda top-level modules in verilog format.
/* ------------------ */
/* common compilation */
/* ------------------ */

/*  Analyze, Elaborate */
/* ------------------- */
include PROJECTD + "/scripts/anal_elab.scr";

/* Schematic Generation */
/* -------------------- */
include PROJECTD + "/scripts/compile.scr";

/* remove unconnected ports */
/* ------------------------ */
include PROJECTD + "/scripts/remove_port.scr";

/* CHANGE CURRENT DESIGN!! */
current_design DESIGN_TOP_PREROUTE


/* save files */
/* ---------- */
VERSION = "_pre_gate";
include PROJECTD + "/scripts/save.scr";

compile -map_effort low

uniquify

/* save files */
/* ---------- */
VERSION = "_gate";
include PROJECTD + "/scripts/save.scr";
Run data base compilation
This scripts reads in precompiled modules and puts them together compiling a wrapper module.
/* ------------------ */
/* common compilation */
/* ------------------ */

/*  read precompiled designs */
/* ------------------------- */
include PROJECTD + "/scripts/read.scr";

/*  read wrapper module */
/* -------------------- */
read -format verilog MODELD + "/" + DESIGN_TOP_PREROUTE + ".v";

/* do not change precompiled modules */
/* --------------------------------- */
sh test -f DESIGN
if (dc_shell_status == 0)
{
   remove_variable dlist > /dev/null
   dlist = execute(-s, sh echo `cat DESIGN `)
}

foreach (dsn, dlist)
{
	current_design dsn

	set_dont_touch dsn
}

if (dc_shell_status == 0)
{
	echo "Error: specified DESIGN not found, quitting"
	list dsn
	quit
} 


/* CHANGE CURRENT DESIGN!! */
current_design DESIGN_TOP_PREROUTE

/* save files */
/* ---------- */
VERSION = "_pre_gate";

include PROJECTD + "/scripts/save.scr";

uniquify

/* Schematic Generation */
/* -------------------- */
compile  -map_effort low

/* remove unconnected ports */
/* ------------------------ */
include PROJECTD + "/scripts/remove_port.scr";


/* save files */
/* ---------- */
VERSION = "_gate";
include PROJECTD + "/scripts/save.scr";
Remove port
Removing of not used ports before writing out EDIF netlist files can be decisive for FPGA emulation because the ALTERA FPGA compiler produces error messages or stops compilation if unused inputs of worse outputs occour.

/* ----------------------------------------------- */
/* remove unconnected ports also processing busses */
/* ----------------------------------------------- */

/* CHANGE CURRENT DESIGN!! */
current_design DESIGN_TOP_PREROUTE

/* remove_unconnected_ports find( -hierarchy cell, "*") -blast_buses; */

sh test -f RMPORTS
if (dc_shell_status == 0)
{
   remove_variable plist > /dev/null
   plist = execute(-s, sh echo `cat RMPORTS `)
}

foreach (dsn, plist)
{
	remove_port dsn
}
Save
To save the compiled design in different formats simultaneously this scripts has proved very helpful.
/* ------------------------------------ */
/* save the design in different formats */
/* ------------------------------------ */
current_design DESIGN_TOP_PREROUTE

write -format db      -hierarchy -output DESIGN_TOP + "/tool_data/FPGAsynopsys/VERSION" + VERSIOND + "/" + DESIGN_TOP_PREROUTE + VERSION + VERSIOND + ".db"  {DESIGN_TOP_PREROUTE}

if (VERSION != "_pre_gate")
{
write -format edif    -hierarchy -output DESIGN_TOP + "/tool_data/FPGAaltera/VERSION"   + VERSIOND + "/" + DESIGN_TOP_PREROUTE                      + ".edf" {DESIGN_TOP_PREROUTE}
write -format verilog -hierarchy -output DESIGN_TOP + "/tool_data/FPGAsynopsys/VERSION" + VERSIOND + "/" + DESIGN_TOP_PREROUTE + VERSION            + ".v"   {DESIGN_TOP_PREROUTE}
}

Project Specific Synthesis Scripts

Synopsys Setup

The following script initializes Synopsys Design Compiler for FPGA2 synthesis.
It calls a standard initialization script and sets up the module specific directory structure.

/* ------------------------------------------------------------------ */
/* Define module-specific directory structure for fpga2_1_0 Synthesis */
/* ------------------------------------------------------------------ */

/* Project Path */
PROJECTD = "/big_second/local_user/barracuda/PreSilicon/design";

/* module name */
MODULE = "fpga2";

/* Top block or verilog module name for place and route */
DESIGN_TOP_PREROUTE = "fpga2_1_0";

/* ----------------- */
/* Global Setup Info */
/* ----------------- */
include PROJECTD + "/scripts/global_setup.scr";


/* ----------------------------------- */
/* Module-specific directory structure */
/* ----------------------------------- */

IPBI  = PROJECTD  + "/ipbridge/tool_data/FPGAsynopsys/VERSION_1/";
SCID  = PROJECTD  + "/sci/tool_data/FPGAsynopsys/VERSION_2/";
SPID  = PROJECTD  + "/spi/tool_data/FPGAsynopsys/VERSION_2/";
I2CD  = PROJECTD  + "/i2c/tool_data/FPGAsynopsys/VERSION_1/";
BLDCD = PROJECTD  + "/bdlc/tool_data/FPGAsynopsys/VERSION_2/";
PWMD  = PROJECTD  + "/pwm_8b8c/tool_data/FPGAsynopsys/VERSION_2/";
TIMD  = PROJECTD  + "/tim_16b8c/tool_data/FPGAsynopsys/VERSION_1/";
KWU   = PROJECTD  + "/kwu16c/tool_data/FPGAsynopsys/VERSION_1/";
CRG   = PROJECTD  + "/crg/tool_data/FPGAsynopsys/VERSION_1/";
PIM   = PROJECTD  + "/pim/tool_data/FPGAsynopsys/VERSION_1/";
PRIM  = PROJECTD  + "/PRIMITIVES/DB/";
MSCAND = PROJECTD + "/mscan/tool_data/FPGAsynopsys/VERSION_2/";

search_path = {". ", std_lib, GLOBAL_VERILOG, LIB_PATH, MODELD, PRIMD, SCRIPTD, IPBI, SCID, SPID, I2CD, BLDCD, PWMD, TIMD, KWU, CRG, PIM, PRIM, MSCAND};
Compile

This scripts uses a list of filenames to read in precompiled modules, puts them together and compiles the wrapper module.

   sh date 

/* run standard compile procedure */
/* ------------------------------ */
include PROJECTD + "/scripts/run_db.scr";

set_dont_touch "PIM" false;
ungroup -simple_names "PIM";

/*  primitives substituted by ALTERA hard instantiated cells */
/*-----------------------------------------------------------*/
remove_design {"bidirec8", "bidirec4"}

/* save files */
/* ---------- */
VERSIOND = "_2";
write -format edif -hierarchy -output DESIGN_TOP + "/tool_data/FPGAaltera/VERSION"   + VERSIOND + "/" + DESIGN_TOP_PREROUTE                      + ".edf" {DESIGN_TOP_PREROUTE}

quit
Design list

The list of designs that is read by the compile script above.

clkgate
ipbridge_1_0
msi_sci
msi_spi
mbus_sb
bdlc_1_0
pwm_8b8c_1_0
tim_16b8c_1_0
kwu16c_1
pim_1_0
crg_1_0
File list

The list of design files required for the compile script.

clkgate.db
ipbridge_1_0_gate_1.db
msi_sci_gate_2.db
msi_spi_gate_2.db
mbus_sb_gate_1.db
bdlc_1_0_gate_2.db
pwm_8b8c_1_0_gate_2.db
tim_16b8c_1_0_gate_1.db
kwu16c_1_gate_1.db
pim_1_0_gate_1.db
crg_1_0_gate_1.db