References

[1]  Altera MaxII+ Help

[2]  http://www.plda.com

[3]  http://www.altera.com

[4]  http://www.ccsf.caltech.edu/A>

[5]  http://www.parsec-design.com

[6]  Motorola Product Proposual: (http://munich.sps.mot.com/MCU_PRJ/BARRACUDA/)

[7]  Motorola Module Specification

[8]  different internet sources

[9]  Mail from Altera Technical Support from 09.10.99

[10]  Perl Reference: http://stuff.mit.edu/perl/perl.html

[11]  http://www.engineersatplay.com

[12]  Wai-Kei Mak and D. F. Wong, On Optimal Board-Level Routing for FPGA-Based Logic Emulation, IEEE Transactions on Computer-aided design of integrated circuits and systems, Vol 16, No 3, March 1997

[13]  Kai Zhu and D. F. Wong, Clock Skew Minimization During FPGA Placement, IEEE Transactions on Computer-aided design of integrated circuits and systems, Vol 16, No 4, April 1997

[14]  Scott Hauck and Gaetano Borriello, Pin Assignment for Multi-FPGA Systems, IEEE Transactions on Computer-aided design of integrated circuits and systems, Vol 16, No 9, September 1997

Acknowledgments

First of all I would like to thank my supervisor, Clemens Müller, who has introduced me into the design process and patiently answered most of my questions.

Some other people have helped me with this and that: Quentin Gunn.